28–29 Jan 2026
Instituto Superior Técnico - Campus Alameda
Europe/Lisbon timezone

Multi-Level Magnetic Tunnel Junctions

29 Jan 2026, 09:45
15m
Departamento de Matemática - PA1 (Instituto Superior Técnico - Campus Alameda)

Departamento de Matemática - PA1

Instituto Superior Técnico - Campus Alameda

Av. Rovisco Pais 1, 1049-001 Lisboa
Workshop 2025/2026

Description

The continuous evolution of computing architectures and the rapid growth of data generation have intensified the demand for non-volatile memory technologies that combine high density, low power consumption, and fast operation. In this context, magnetoresistive random-access memory (MRAM), based on magnetic tunnel junctions (MTJs), has emerged as a promising candidate. However, conventional MTJs are inherently limited to two resistance states, restricting information storage to a single bit per cell.

This work focuses on the development and optimization of multi-level MTJs capable of exhibiting more than two stable resistance states, enabling multi-bit storage within a single memory cell. In particular, a shape-anisotropy-based approach is explored, employing a free layer composed of two crossing ellipses (TCE) that can stabilize four distinct remanent magnetic states, combined with a single-ellipse fixed layer. Writing is achieved through spin–orbit torque (SOT), which allows physical separation between write and read paths, reducing electrical stress on the tunnel barrier.

The theoretical foundations of MTJs and the main SOT mechanisms are reviewed, followed by the presentation of a fabrication process compatible with microfabrication at INESC-MN, structured into four lithography levels. Furthermore, micromagnetic simulations performed using MuMax3 demonstrate the stabilization of four remanent states in the TCE free layer and the corresponding normalized MTJ electrical readout.

The results confirm the potential of shape-anisotropy-based multi-level MTJs as key building blocks for high-density non-volatile memories and emerging neuromorphic computing architectures. This work establishes a solid foundation for future experimental fabrication, electrical characterization, and further device optimization.

Field of Research/Work Condensed Matter and Materials

Author

Presentation materials