28–29 Jan 2025
Instituto Superior Técnico - Campus Alameda
Europe/Lisbon timezone

Nanoelectronic chip design: from physics principles to circuit design for production

29 Jan 2025, 11:00
12m
Anfiteatro PA1 (Instituto Superior Técnico - Campus Alameda)

Anfiteatro PA1

Instituto Superior Técnico - Campus Alameda

Av. Rovisco Pais 1, 1049-001 Lisboa

Speaker

Vasco Nunes (Instituto Superior Técnico)

Description

Conventional computer hardware suffers from the “memory wall” or von Neumann bottleneck, where data transfer between memory arrays and processors leads to significant latency and energy inefficiencies. A promising solution to this issue is in-memory computing hardware, which integrates memory and computation in the same unit. Neuromorphic computing is one such architecture, designed to emulate the structure and function of the brain. This approach requires electronic components that replicate biological elements like neurons and synapses. Memristors—nanoscale resistors with non-volatile, analog conductance states, which can be tuned by an electric bias—are ideal candidates for these roles, acting as synthetic synapses within neuromorphic systems.

This work focuses on the study of memristors, aiming to provide a solid understanding of the device. Cadence Virtuoso, an industry-standard tool for professional circuit design, is used to model and simulate the memristor at the circuit level. Additionally, Si/Ag-based memristors are fabricated at INESC MN, providing a comprehensive understanding of the nano- and microfabrication process. This foundational knowledge serves as a basis for future research in neuromorphic nanoelectronic circuits.

Primary author

Vasco Nunes (Instituto Superior Técnico)

Presentation materials